Content addressable memory (CAM) arrays and cells having low power requirements

ABSTRACT

A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V CC  supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the V CC  supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the V CC  supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the V CC  supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the V CC  supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.

This application is a divisional of U.S. application Ser. No.10/246,586, filed Sep. 18, 2002, now abandoned, which is a reissue ofU.S. application Ser. No. 09/185,057, filed Nov. 2, 1998, now U.S. Pat.No. 6,128,207.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to content addressable memory (CAM) cells.More specifically, the present invention relates to nine transistor CAMcells and methods for operating these cells in an array.

2. Discussion of Related Art

CAM cells are defined as memory cells that are addressed in response totheir content, rather than by a physical address within an array. FIG. 1is a block diagram of a conventional memory array formed using twelveCAM cells. The CAM cells are labeled M_(X,Y), where X is the row of thearray, and Y is the column of the array. Thus, the array includes CAMcells M_(0,0) to M_(2,3). Each of the CAM cells is programmed to store adata value. In the described example, the data value stored in each CAMcell is indicated by either a “0” or a “1” in brackets. For example, CAMcells M_(0,0), M_(0,1), M_(0,2) and M_(0,3) store data values of 0, 1, 0and 0, respectively. Each row of CAM cells is coupled to a common matchline. For example, CAM cells M_(0,0), M_(0,1), M_(0,2) and M_(0,3) arecoupled to match line MATCH₀.

The array of CAM cells is addressed by providing a data value to eachcolumn of CAM cells. Thus data values D₀, D₁, D₂ and D₃ are provided tocolumns 0, 1, 2 and 3, respectively. Note that complementary data valuesD₀#, D₁#, D₂# and D₃# are also provided to columns 0, 1, 2 and 3,respectively. If the data values stored in a row of the CAM cells matchthe applied data values D₀-D₃, then a match condition occurs. Forexample, if the data values D₀, D₁, D₂ and D₃ are 0, 1, 0 and 0,respectively, then the data values stored in the CAM cells of row 0match the applied data values. Under these conditions, the MATCHo signalis asserted high. Because the applied data values D₀, D₁, D₂ and D₃ donot match the data values store in the CAM cells of rows 1 or 2, theMATCH₁ and MATCH₂ signals are de-asserted low. The match signalsMatch₀-MATCH₂ can be used for various purposes, such as implementingvirtual addressing, in a manner (known to those skilled in the art.

Many different types of CAM cells have been designed. Importantconsiderations in the design of a CAM cell include: the number oftransistors required to implement the cell, the power required tooperate the CAM cell, and the speed of the CAM cell. In general, it isdesirable to have a CAM cell that is implemented using a relativelysmall number of transistors, such that the layout area of the CAM cellis minimized. It is also desirable for the CAM cell to have a low powerrequirement and a fast operating speed.

FIG. 2 is a circuit diagram of a conventional nine tune transistor (9-T)CAM cell 10. CAM cell 10 is described in detail in U.S. Pat. No.4,723,224. CAM cell 10 includes a conventional static random accessmemory (SRAM) cell 12 and as exclusive OR (XOR) gate 14. SRAM cell 12includes access transistors 20 and 22, and cross-coupled inverters 16and 18. Access transistors 20 and 22 are coupled to word line 28 and bitlines 24 and 26, as illustrated. Driver circuitry 36 provides a datavalue (D) and the inverse of the data value (D#) to bit lines 24 and 26,respectively, during write and compare operations.

SRAM cell 12 is written like a conventional SRAM cell. That is, a logichigh value is applied to word line 28, and data values D and D# areapplied to bit lines 24 and 26, respectively. As a result, the datavalues D and D# are latched by inverters 16 and 18, such that the datavalue D is provided as the output of inverter 18, and the inverted datavalue D# is provided at the output of inverter 16.

XOR gate 14 includes n-channel transistors 30 and 32, which areconnected in series between bit lines 24 and 26. The output terminal ofinverter 16 is connected to the gate of transistor 30, such that theinverted data value D# stored in SRAM cell 12 is provided to the gate oftransistor 30. Similarly, the output terminal of inverter 18 isconnected to the gate of transistor 32, such that the data value Dstored in SRAM cell 12 is provided to the gate of transistor 30.Transistors 30 and 32 are commonly connected at node 34, which forms theoutput terminal of XOR gate 14. Node 34 is connected to the gate ofn-channel transistor 38. Transistor 38 has a source coupled to groundline 42, and a drain coupled to match line 40.

CAM cell 10 performs a compare operation as follows. Driver circuitry 36applies a comparison data value (C) and its complement (C#) to bit lines24 and 26, respectively. If the comparison data value C matches the datavalue D stored in SRAM cell 12, then node 34 is connected to receive alogic “0” signal. As a result, transistor 38 is turned off, therebyisolating match line 40 from ground line 42. Under these conditions,match line 40 retains a pre-charged logic high value.

Conversely, if the comparison data value C does not match the data valueD stored in SRAM cell 12, then node 34 is connected to receive a logic“1” signal. As a result, transistor 38 is turned on, thereby couplingmatch line 40 to ground line 42. Under these conditions, match line 40is pulled down toward ground.

CAM cell 10 exhibits relatively high power consumption because the samedriver circuitry 36 is used to supply the write data values as well asthe comparison data values. Driver circuitry 36 is powered by the V_(CC)supply voltage, such that both the write and comparison data values havelogic high values of V_(CC). Moreover, the compare operation of CAM cell10 is relatively slow because the capacitance of SRAM cell 12 is coupledto bit lines 24 and 26 during the compare operation.

It would therefore be desirable to have an improved CAM cell whichallows a compare operation to be carried out using a supply voltage lessthan the V_(CC) supply voltage. It would also be desirable for theimproved CAM cell to have bit lines that are not coupled to thecapacitance introduced by an SRAM cell during a compare operation. Itwould also be desirable for the improved CAM cell to be implementedusing fewer transistors than conventional CAM cell 10. It would furtherbe desirable for the improved CAM cell to have global and local maskingcapabilities.

SUMMARY

Accordingly, the present invention provides a CAM cell that implements amatch line having a signal swing equal to one transistor thresholdvoltage, or about 0.3 Volts. The operating power of the CAM cell of thepresent invention is relatively low because the match line onlyundergoes a small voltage swing during a compare operation.

A CAM in accordance with the present invention includes an SRAM cellthat operates in response to a V_(CC) supply voltage. One or moreread/write bit lines are coupled to the SRAM cell, thereby allowing readand write data values to be transferred to and from the SRAM cell. TheV_(CC) and ground voltage supplies provide signals to the read/write bitlines. That is, the signals applied to the read/write bit lines varybetween a high voltage of V_(CC) and a low voltage of 0 Volts.

One or more comparison bit lines are coupled to receive a comparisondata value. The signals transmitted on the comparison bit lines have asignal swing that is less than the V_(CC) supply voltage. In oneembodiment, the signal swing on the comparison bit lines is equal to twotimes the transistor threshold voltage. Thus, if the transistorthreshold voltage is equal to 0.3 Volts, then the signal swing on thecomparison bit lines is equal to 0.6 Volts. Because the comparison bitlines are not directly connected to the SRAM cell, the capacitance ofthe SRAM cell is advantageously not coupled to the comparison bit lines.This improves both operating speed and power consumption of the CAMcell.

Moreover, the signals transmitted on the comparison bit lines aregenerated by a bit line control circuit that is powered in response to asupply voltage V_(CC1) that is significantly lower than the V_(CC)supply voltage. In one embodiment, the supply voltage V_(CC1) can have avalue as low as 0.9 Volts. By lowering the supply voltage required toperform a compare operation, the power of operating the CAM isadvantageously reduced.

A sensor circuit is provided for comparing the data value stored in theCAM cell with the comparison data value provided on the comparison bitlines. The sensor circuit pre-charges the match line prior to a compareoperation. If the data value stored in the CAM cell does not match thecomparison data value, the match line is pulled down. The signal swingof the match line is smaller than the V_(CC) supply voltage. In oneembodiment, the signal swing on the match line is equal to transistorthreshold voltage, or 0.3 Volts.

The sensor circuit monitors the voltage on the match line to determinewhether the comparison data value matches the data value stored in theCAM cell (a match condition), or whether the comparison data value failsto match the data value stored in the CAM cell (a no-match condition).The sensor circuit converts the small swing signal on the match line toa large swing output signal. This output signal has a signal swing equalto the V_(CC) supply voltage.

In one embodiment of the invention, a bit line control circuit isprovided to control the voltages on the comparison bit lines. The bitline control circuit equalizes the voltages on the comparison bit linesto an intermediate voltage prior to each compare operation. As a result,less power is consumed during the compare operation. In one embodimentthe intermediate voltage is equal to a transistor threshold voltage(e.g., 0.3 Volts).

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional array of CAM cells;

FIG. 2 is a circuit diagram of a conventional nine transistor CAM cell;

FIG. 3, which consists of FIGS. 3A and 3B as illustrated, is a schematicdiagram of a 2×2 array of nine-transistor CAM cells in accordance withone embodiment of the present invention;

FIGS. 4A and 4B are schematic diagrams of diode connected transistorsthat can be used in various embodiments of the invention;

FIG. 4C is a schematic diagram of a diode-connected transistor and alocal masking transistor in accordance with another embodiment of theinvention;

FIG. 5 is a schematic diagram of the sensor circuit of FIG. 3 inaccordance with one embodiment of the present invention;

FIG. 6 is a schematic diagram of the bit line control circuit of FIG. 3in accordance with one embodiment of the present invention;

FIG. 7A is a schematic diagram of an 8-T CAM cell in accordance with onevariation of the present invention;

FIG. 7B is a schematic diagram of an 8-T CAM cell in accordance withanother variation of the present invention;

FIG. 8, which consists of FIGS. 8A and 8B as illustrated, is a schematicdiagram of a 2×2 array of nine-transistor CAM cells in accordance withanother embodiment of the present invention;

FIG. 9 is a schematic diagram of the sensor circuit of FIG. 8 inaccordance with one embodiment of the present invention;

FIG. 10A is a schematic diagram of an 8-T CAM cell in accordance withone variation of the present invention; and

FIG. 10B is a schematic diagram of an 8-T CAM cell in accordance withanother variation of the present invention.

DETAILED DESCRIPTION

FIG. 3, which consists of FIGS. 3A and 3B as illustrated, is a schematicdiagram of an array of nine-transistor CAM cells 100, 200, 300 and 400.CAM cell 100 includes read/write bit lines 101-102, compare bit lines103-104, word line 105, p-channel transistors 110-111, n-channeltransistors 112-118, and diode element 119. P-channel transistors110-111 and n-channel transistors 112-115 are connected as asix-transistor SRAM cell. More specifically, transistors 110 and 112 areconnected in series between the V_(CC) supply terminal and the groundsupply terminal to form a first inverter 121. Similarly, transistors 111and 113 are connected between the V_(CC) supply terminal and the groundsupply terminal to form a second inverter 122. Inverters 121 and 122 arecross-coupled, thereby forming a storage latch that stores a data valueD₀. The output terminal of inverter 121 is labeled node N1, and theoutput terminal of inverter 122 is labeled node N2.

N-channel transistor 114 is coupled as an access transistor between nodeN1 and read/write bit line 101. Similarly, n-channel transistor 115 iscoupled as an access transistor between node N2 and read/write bit line102. Read/write bit lines 101 and 102 are coupled to receive read/writedata values D₀ and D₀#, respectively, from column decoder circuitry (notshown). Read/write data value D₀ has a logic high value of V_(CC) and alogic low level of 0 Volts during a write operation. Similarly,read/write data value D₀ has a logic high value of V_(CC) and a logiclow level of V_(CC)−CV during a read operation (where CV is about 300mV). The gates of access transistors 114 and 115 are commonly connectedto word line 105. Word line 105 is coupled to receive word line signalWL₀ from row decoder circuitry (not shown). The word line signal VL₀ hasa logic high value of V_(CC) and a logic low value of 0 Volts.

Comparison bit lines 103 and 104 are coupled to receive comparison datavalues CD₀ and CD₀# from bit line control circuit 120, which isdescribed in more detail below in connection with FIG. 5. Comparisondata value CD₀ has a logic high value of 0.6 Volts, a logic low value of0 Volts, and a pre-charge value of 0.3 Volts. Thus, the voltages usedduring a comparison operation are much lower than the V_(CC) supplyvoltage. Moreover, bit line control circuit 120 operates in response toa supply voltage V_(CC1), which is much less than the V_(CC) supplyvoltage. In the described embodiment, the V_(CC1) supply voltage isabout 0.9 Volts. As a result, the power requirements of CAM cell 100 aremuch less than a conventional 9-T CAM cell. In addition, the bit lines103-104 used to perform a comparison are not coupled to the 6-T SRAMcell. As a result, the comparison operation is not burdened by thecapacitance introduced by the 6-T SRAM cell. N-channel transistors 116and 117 are connected in series between bit lines 103 and 104.Transistors 116 and 117 are commonly connected at node N3. The gates oftransistors 116 and 117 are connected to nodes N1 and N2, respectively.Node N3 is coupled to a match sense line 150 through diode element 119and n-channel transistor 118. Match sense line 150 is coupled to sensorcircuit 130.

Diode element 119 can be implemented in various ways, including aconventional p-n junction or a diode-connected transistor. FIGS. 4A and4B are schematic diagrams of diode connected transistors 119A and 119B,respectively, that can be used to implement diode element 119 inaccordance with various embodiments of the invention. Thus, diodeelement 119 is counted as one of the nine transistors of CAM cell 100.As described in more detail below, n-channel transistor 118 is anoptional local masking transistor. Because local masking transistor 118is optional, this transistor is typically not included in determiningthe transistor count of CAM cell 100. Local masking transistor 118 iscoupled to receive a local mask enable signal LM#₁. FIG. 4c is aschematic diagram illustrating local masking transistor 118 coupled todiode connected transistor 119A in accordance with another variation.

CAM cell 200 includes read/write bit lines 201-202, comparison bit lines203-204, word line 105, p-channel transistors 210-211, n-channeltransistors 212-218, and diode element 219. The elements of CAM cell 200are connected in the same manner as the elements of CAM cell 100. CAMcell 200 is connected to word line 105 in the same manner as CAM cell100. Similarly, CAM cell 200 is connected to match sense line 150 in thesame manner as CAM cell 100. Read/write bit lines 201 and 202 of CAMcell 200 are coupled to receive read/write data values D₁ and D₁# fromcolumn control circuitry (not shown). Comparison bit lines 203 and 204of CAM cell 200 are coupled to receive comparison data values CD₁ andCD₁# from bit line control circuit 220.

CAM cell 300 includes read/write bit lines 101-102, comparison bit lines103-104, word line 106, p-channel transistors 310-311, n-channeltransistors 312-318, and diode element 319. Similarly, CAM cell 400includes read/write bit lines 201-202, comparison bit lines 203-204,word line 106, p-channel transistors 410-411, n-channel transistors412-418, and diode element 419. The elements of CAM cells 300 and 400are connected in the same manner as the elements of CAM cell 100. CAMcells 300 and 400 are coupled to a second word line 106 in the samemanner that CAM cells 100 and 200 are coupled to word line 105.Similarly, CAM cells 300 and 400 are coupled to a second match senseline 151 in the same manner that CAM cells 100 and 200 are coupled tomatch sense line 150. Match sense line 151 is coupled to a sensorcircuit 131, which is identical to sensor circuit 130. Note that CAMcells 100 and 300 share bit lines 101-104. Similarly, CAM cells 200 and400 share bit lines 201-204.

Although the array illustrated in FIG. 3 only has two rows and twocolumns of CAM cells, it is understood that this array can be expandedto include many more rows and columns of CAM cells. The manner ofexpansion is obvious in view of the 2×2 array of CAM cells 100, 200, 300and 400 shown in FIG. 3. In a particular example, an array of CAM cellsincludes eight rows and seventy-two columns of CAM cells.

Data values are written to a row of CAM cells (e.g., CAM cells 100 and200), as follows. The voltage WL₀ on word line 105 is pulled up to theV_(CC) supply voltage (e.g., 2.5 Volts) by the row decoder circuitry. Asa result, access transistors 114-115 and 214-215 are turned on, therebycoupling bit lines 101-102 and 201-202 to the storage latches in CAMcells 100 and 200. The voltage WL₁ on the second word line 106 is pulleddown to 0 Volts, thereby turning off access transistors 314-315 and414-415 in CAM cells 300 and 400. As a result, bit lines 101-102 and201-202 are isolated from the storage latches in CAM cells 300 and 400.

The column decoder circuitry applies write data values D₀, D₀#, D₁, andD₁# to bit lines 101, 102, 201 and 202, respectively. These write datavalues have a logic high value equal to the V_(CC) supply voltage and alogic low value of 0 Volts. In the described example, data values D₀,D₀#, D₁, and D₁# have values of V_(CC), 0, 0 and V_(CC), respectively.The write data values D₀, D₀#, D₁, and D₁# are transmitted throughturned on access transistors 114-115 and 214-215 to the storage latchesin CAM cells 100 and 200. The word line signal WL₀ is then de-assertedlow, thereby turning off access transistors 114-115 and 214-215, andlatching the write data values D₀, D₀#, D₁, and D₁# in the storagelatches of CAM cells 100 and 200. Write operations are thereforeperformed in the same manner as in a conventional six-transistor SRAMarray. In the present example, nodes N1, N2, N4 and N5 store voltages ofV_(CC), 0 Volts, 0 Volts and V_(CC), respectively.

Data values are read from a row of CAM cells (e.g., CAM cells 100 and200), as follows. The column decoder circuitry applies the V_(CC) supplyvoltage to read/write bit lines 101, 102, 201 and 202. The voltage WL₀on word line 105 is pulled up to the V_(CC) supply voltage (e.g., 2.5Volts) by the row decoder circuitry. As a result, access transistors114-115 and 214-215 are turned on, thereby coupling bit lines 101-102and 201-202 to the storage latches in CAM cells 100 and 200. The voltageWL₁ on the second word line 106 is pulled down to 0 Volts, therebyturning off access transistors 314-315 and 414-415 in CAM cells 300 and400. As a result, bit lines 101-102 and 201-202 are isolated from thestorage latches in CAM cells 300 and 400.

In the present example, nodes N2 and N4 are pulled down throughtransistors 113 and 212, respectively. When access transistors 115 and214 are turned on, bit lines 102 and 201 are pulled down by transistors113 and 212, respectively. Nodes N2 and N4 are pulled down to V_(CC)-CVat this time, where CV is approximately 300 mV. Bit lines 101 and 202are not pulled down in this manner. Sense amplifiers (not shown) coupledto bit lines 101-102 and 201-202 sense the different voltages on thesebit lines to identify the data values stored by CAM cells 100 and 200.Read operations are therefore performed in the same manner as in aconventional six-transistor SRAM array.

During standby conditions, word lines 105 and 106 are maintained at 0Volts, thereby isolating the CAM cells 100, 200, 300 and 400 fromread/write bit lines 101-102 and 201-202. Read/write bit lines 101-102and 201-202 are held at either V_(CC) or 0 Volts during standbyconditions.

A compare operation is performed as follows. During a compare operation,word lines 105 and 106 are maintained at a voltage of 0 Volts, therebyisolating the CAM cells 100, 200, 300 and 400 from bit lines 101-102 and201-202. Read/write bit lines 101-102 and 201-202 are held at eitherV_(CC) or 0 Volts during a compare operation. A compare operation issimultaneously performed within each CAM cell of the array, unless thereis global or local masking that inhibits the compare operation withinthe CAM cell. For purposes of clarity, a compare operation within CAMcell 100 is described in detail. The compare operations performed withinCAM cells 200, 300 and 400 are identical to the compare operationperformed within CAM cell 100.

The compare operation within CAM cell 100 is controlled by bit linecontrol circuit 120 and sensor circuit 130. In general, the data valuein the storage latch of CAM cell 100 turns on one and only one oftransistors 116 and 117, thereby coupling one of the comparison bitlines 103-104 to node N3. Prior to the comparison operation, node N3 andcomparison bit lines 103-104 are maintained at 0.3 Volts (assuming thereis no global masking enabled by bit line control circuit 120). Localmasking transistor 118 is turned on (assuming there is no local maskingenabled within CAM cell 100). Sensor circuit 130 maintains match senseline 150 at a voltage of 0.6 Volts. A 0.3 Volt forward voltage droptherefore exists across diode-connected transistor 119A.

To initiate the comparison operation, bit line control circuit 120applies comparison data values CD₀ and CD₀# to comparison bit lines 103and 104, respectively. The logic high comparison data value has avoltage of 0.6 Volts, and the logic low comparison data value has avoltage of 0 Volts. If the comparison data value matches the data valuestored in CAM cell 100, then a voltage of 0.6 Volts is applied to nodeN3. Under these conditions, the voltage on match sense line 150 remainsat 0.6 Volts. If the comparison data value does not match the data valuestored in CAM cell 100, then a voltage of 0 Volts is applied to node N3.Under these conditions, the voltage on match sense line 150 is pulleddown to 0.3 Volts. Sensor circuit 130 senses the voltage on match senseline 150, and indicates a match condition if match sense line 150 ismaintained at 0.6 Volts, and indicates a no-match condition if matchsense line 150 is pulled down to 0.3 Volts. Because the full signalswing on match sense line 150 is equal to 0.3 Volts, and because thecomparison bit lines are operated at voltages much less than the V_(CC)supply voltage, the power requirements of a compare operation areadvantageously very low in CAM cell 100.

Local masking signal LM#₁ is an active low signal. If the local maskingsignal LM#₁ has a logic low value, local masking transistor 118 isturned off, thereby isolating node N3 from match sense line 150. Underthese conditions, match sense line is maintained at 0.6 Volts,regardless of the results of the comparison within CAM cell 100. CAMcell 100 therefore performs as if a match condition exists, regardlessof the results of the comparison within CAM cell 100. In this manner,local masking transistor 118 enables CAM cell 100 to be effectivelymasked from the comparison operation. Although FIG. 3 indicates thatlocal masking transistor 118 is coupled between diode 119 and match line150, it is understood that local masking transistor 118 can be coupledbetween diode 119 and node N3 to achieve similar results. FIG. 4C is aschematic diagram illustrating another possible arrangement ofdiode-connected transistor 119A and local masking transistor 118. Othervariations are apparent to those of ordinary skill in the art.

Bit line control circuit 120 and sensor circuit 130 will now bedescribed in more detail. FIG. 5 is a schematic diagram of sensorcircuit 130. Sensor circuit 130 includes inverters 501-502, currentsources 503-504, NAND gate 505 and n-channel transistors 311-511, whichare connected as illustrated. During a pre-charge period before thecompare operation is performed, the CLK1 and CLK2 signals have logic lowvalues. The logic low CLK2 signal causes transistor 511 to turn on,thereby coupling the V_(CC1) supply voltage to the drain of transistor513. In the described example, the V_(CC1) supply voltage is equal toapproximately three times the threshold voltage of an n-channeltransistor, or about 0.9 Volts. The logic low CLK1 signal causes NANDgate 505 to provide a logic high output signal (e.g., 2.5 Volts) to thegate of transistor 512, thereby turning on this transistor. As a result,transistor 512 also helps to pull up the voltage on the drain oftransistor 513 to the V_(CC1) supply voltage.

Under these conditions, transistors 514 and 515 are turned on by currentsource 504. Each of transistors 514 and 515 has a threshold voltage of0.3 Volts. As a result, the voltage on match sense line 150 is held at0.6 Volts. At this time, the voltage on node N3 is equal to 0.3 Volts,or one threshold voltage below the voltage on match sense line 150.

The compare operation begins when the CLK2 signal goes high. The CLK2signal transitions to a logic high state shortly before the CLK1 signaltransitions to a logic high state. As a result, the output signalprovided by NAND gate 505 remains high for a short time after the CLK2signal goes high. This ensures that transistor 512 remains on while theCLK2 signal goes high, thereby preventing noise conditions from pullingdown the voltage on match sense line 150. The CLK1 signal thentransitions to a logic high value, such that the output voltage providedby NAND gate 505 is determined by the state of the voltage on matchsense line 150. At this time, node N3 is either pulled up to 0.3 Volts(if a match condition exists) or pulled down to 0 Volts (if a no-matchcondition exists).

As described in more detail below, during a match condition node N3 willbe coupled to a comparison bit line having a voltage of 0.6 Voltsthrough either transistor 116 or transistor 117. Under these conditions,no current flows through transistor 513. As a result, the gate oftransistor 513 is maintained at about 0.6 Volts. This 0.6 Volt signalrepresents a logic low input signal to NAND gate 505. As a result, NANDgate 505 provides a logic high output signal to transistor 512.Transistor 512 therefore remains on (even though there is no currentflow). If the signal on match sense line 150 is pulled low by noise,then current source 503 will pull the voltage on match sense line 150back up to 0.6 Volts through turned on transistor 512.

The logic high output of NAND gate 505 is also provided to inverter 502.In response, inverter 502 provides a logic low output signal having avoltage equal to the ground supply voltage (e.g., 0 Volts). This outputsignal is used to indicate a match condition to an encoder circuit (notshown). As described in more detail below, during a no-match conditionnode N3 will be coupled to a comparison bit line having a voltage of 0Volts through either transistor 116 or transistor 117. As a result, nodeN3 is pulled down to 0 Volts. Under these conditions, current will flowthrough transistor 513. This current is greater than the currentprovided by current source 503. As a result, the voltage of match senseline 150 is pulled down to 0.3 Volts (i.e., one threshold voltagegreater than the voltage on node N3). The 0.3 Volt signal on match senseline 150 causes the voltage on the gate of transistor 513 to be pulledup to the V_(CC) supply voltage (e.g., 2.5 Volts) by current source 504.This V_(CC) supply voltage represents a logic high input signal to NANDgate 505. Consequently, NAND gate 505 provides a logic low output signalto the gate of transistor 512. As a result, transistor 512 is turnedoff, thereby preventing DC current flow through transistor 513.

The logic low output of NAND gate 505 is also provided to inverter 502.In response, inverter 502 provides a logic high output signal having avoltage equal to the V_(CC) supply voltage (e.g., 2.5 Volts). Thisoutput signal is used to indicate a no-match condition to an encodercircuit (not shown).

Although the operation of sensor circuit 130 has been described inconnection with a single CAM cell 100, it is understood that a matchcondition must exist in all of the CAM cells coupled to match sense line150 in order for sensor circuit 130 to provide a logic high outputsignal to the encoder. Conversely, if a no-match condition exists in anyone of the CAM cells coupled to match sense line 150, then sensorcircuit 130 will provide a logic low output signal to the encoder.

FIG. 6 is a schematic diagram of bit line control circuit 120. Bit linecontrol circuit 121 is identical to bit line control circuit 120. Bitline control circuit 120 includes inverters 601-609, NAND gates 611-612,n-channel transistors 621-630 and current source 631, which areconnected as illustrated. In general, bit line control circuit 120provides voltages on comparison bit lines 103-104 in response to acomparison data input value D_(IN), the clock signal CLK2, and a globalmasking signal GM#.

Bit line control circuit 120 operates as follows. Transistors 628-630and current source 631 are connected to form a regulated voltage source640. Current source 631, which operates in response to the V_(CC) supplyvoltage, turns on transistors 629 and 630. Each of transistors 629 and630 has a threshold voltage of 0.3 Volts. As a result, the voltage onvoltage supply line 650 is held at 0.6 Volts. Transistor 628, which iscoupled to the V_(CC1) voltage supply (0.9 Volts), is turned on to helppull up voltage supply line 650 to 0.6 Volts. In the describedembodiment, the voltage on voltage supply line 650 is selected to beequal to two times the threshold voltage of an n-channel transistor(i.e., 0.3 Volts).

Global masking signal GM# is an active low signal. When the globalmasking signal GM# has a logic low value, inverters 602-604 provide alogic high signal to transistors 621 and 622, thereby turning on thesetransistors. The logic low GM# signal causes transistors 623-626 to beturned off. Transistor 627 is either turned off or turned on, dependingon the state of the CLK2 signal. Under these conditions, both ofcomparison bit lines 103 and 104 are connected to receive a voltage of0.6 Volts from voltage supply line 650. If both of comparison bit lines103 have a voltage of 0.6 Volts, then all of the CAM cells in the columnserved by bit line control circuit 120 will indicate a match conditionduring a compare operation. As a result, the entire column iseffectively masked during such a compare operation.

When the global masking signal GM# is de-asserted high, transistors 621and 622 are turned off. During this time, the CLK2 signal can have alogic low or logic high value. A pre-charge operation is performed ifthe CLK2 signal has a logic low value, and a compare operation isperformed if the CLK2 signal has a logic high value. If the CLK2 signalhas a logic low value, transistor 627 is turned on, thereby connectingcomparison bit lines 103 and 104. The logic low CLK2 signal furthercauses transistors 623-626 to turn off, thereby isolating comparison bitlines 103 and 104 from voltage supply line 650 and the ground voltagesupply. As a result, the voltages on both bit lines 103 and 104 areequalized at 0.3 Volts by sensor circuit 130 during the pre-chargeoperation. Note that the comparison data input value D_(IN) does nothave any effect on transistors 623-627 when the CLK2 signal has a logiclow value.

A compare operation occurs when the CLK2 signal transitions to a logichigh value (and the GM# signal is de-asserted high). Under theseconditions, transistors 621-622 and 627 are turned off. Comparison datainput value D_(IN) is asserted at this time. A comparison data inputvalue D_(IN) having a logic high state will turn on transistors 623 and624 (and turn off transistors 625 and 626), thereby applying 0.6 Voltsto comparison bit line 103 and 0 Volts to comparison bit line 104.Conversely, a comparison data input value D_(IN) having a logic lowstate will turn on transistors 625 and 626 (and turn off transistors 623and 624), thereby applying 0.6 Volts to comparison bit line 104 and 0Volts to comparison bit line 103.

Although the present invention has been described in connection withparticular embodiments, other embodiments are possible and areconsidered to be within the scope of the present invention. FIG. 7A is aschematic diagram of an 8-T CAM cell 700A in accordance with onevariation of the present invention. Similar elements in CAM cell 100(FIG. 3) and CAM cell 700A are labeled with similar reference numbers.CAM cell 700A includes the same elements as CAM cell 100, with theexception of access transistor 115 and bit line 102, which are notpresent in CAM cell 700A. CAM cell 700A is written and read through bitline 101 and access transistor 114. The compare operation of CAM cell700A is identical to the compare operation of CAM cell 100. CAM cell700A advantageously uses one less transistor and one less bit line thanCAM cell 100. Note that the above-described variations of CAM cell 100can also be applied to CAM cell 700A.

FIG. 7B is a schematic diagram of an 8-T CAM 700B in accordance withanother variation of the present invention. Similar elements in CAM cell100 (FIG. 3) and CAM cell 700B are labeled with similar referencenumbers. CAM cell 700B includes the same elements as CAM cell 100, withthe exception of access transistor 115 and bit lines 102 and 103, whichare not present in CAM cell 700B. CAM cell 700B is written and readthrough bit line 101 and access transistor 114. The compare operation ofCAM cell 700B is similar to the compare operation of CAM cell 100.However, the comparison data value CD₀ is provided on bit line 101 inthis variation. Selection circuitry (not shown) is provided toselectively couple bit line 101 to the above-described column selectcircuitry (not shown) during a read or a write operation, or to the bitline control circuit 120 during a compare operation. CAM cell 700Badvantageously uses one fewer transistor and two fewer bit lines thanCAM cell 100. Note that the above-described variations of CAM cell 100can also be applied to CAM cell 700B.

FIG. 8, which consists of FIGS. 8A and 8B as illustrated, is a schematicdiagram of an array of nine-transistor CAM cells 1000, 2000, 3000 and4000. Because CAM cells 1000, 2000, 3000 and 4000 are similar to CAMcells 100, 200, 300 and 400 (FIG. 3), similar elements in FIGS. 3 and 8are labeled with similar reference numbers. CAM cell 1000 replaces diodeelement 119, local masking transistor 118 and match sense line 150 ofCAM cell 100 with match transistor 1190, local masking transistor 1180and match sense lines 1500 and 1510. Transistors 1180 and 1190 areconnected in series between match sense lines 1500 and 1510. The gate ofmatch transistor 1190 is coupled to node N3. Both of match sense lines1500 and 1510 are connected to sensor circuit 1300.

CAM cells 2000, 3000 and 4000 include similar match transistors 2190,3190 and 4190 and similar local masking transistors 2180, 3180 and 4180.CAM cells 3000 and 4000 share match sense lines 1520 and 1530, which inturn, are connected to sensor circuit 1310.

Bit line control circuits 1200 and 2200 are connected to comparison bitlines 103-104 and 203-204, respectively.

Although the array illustrated in FIG. 8 only has two rows and twocolumns of CAM cells, it is understood that this array can be expandedto include many more rows and columns of CAM cells. The manner ofexpansion is obvious in view of the 2×2 array of CAM cells 1000, 2000,3000 and 4000 shown in FIG. 8.

Because CAM cells 1000, 2000, 3000 and 4000 are identical, only CAM cell1000 is described in detail. Similarly, because sensor circuits 1300 and1310 are identical, only sensor circuit 1300 is described in detail.

CAM cell 1000 reverses the polarity of the comparison data values CD₀and CD₀# provided by bit line control circuit 120, such that comparisondata value CD₀# is applied to comparison bit line 103, and comparisondata value CD₀ is applied to comparison bit line 104. In addition,voltage supply line 650 is directly connected to the V_(CC1) supplyvoltage of 0.9 Volts (3V_(T)) instead of to regulated voltage source640. Otherwise, the bit line control circuit 1200 is identical to bitline control circuit 120 (FIG. 6).

Read, write and standby operations are performed within CAM cell 1000 inthe same manner described above in connection with CAM cell 100.

A compare operation is performed within CAM cell 1000 as follows. Duringa compare operation, word lines 105 and 106 are maintained at a voltageof 0 Volts, thereby isolating the CAM cells 1000, 2000, 3000 and 4000from bit lines 101-102 and 201-202. Read/write bit lines 101-102 and201-202 are held at either V_(CC) or 0 Volts during a compare operation.A compare operation is simultaneously performed within each CAM cell ofthe array, unless there is global or local masking that inhibits thecompare operation within the CAM cell. For purposes of clarity, acompare operation within CAM cell 1000 is described in detail. Thecompare operations performed within CAM cells 2000, 3000 and 4000 areidentical to the compare operation performed within CAM cell 1000.

The compare operation within CAM cell 1000 is controlled by bit linecontrol circuit 1200 and sensor circuit 1300. In general, the data valuein the storage latch of CAM cell 1000 turns on one and only one oftransistors 116 and 117, thereby coupling one of the comparison bitlines 103-104 to node N3. Prior to the comparison operation, node N3 andcomparison bit lines 103-104 are maintained at 0.3 Volts (assuming thereis no global masking enabled by bit line control circuit 1200). Localmasking transistor 1180 is turned on (assuming there is no local maskingenabled within CAM cell 1000). Sensor circuit 1300 maintains match senselines 1500 and 1510 at 0.3 Volts.

To initiate the comparison operation, bit line control circuit 1200applies comparison data values CD₀ and CD₀# to comparison bit lines 104and 103, respectively. The logic high comparison data value has avoltage of 0.9 Volts (i.e., V_(CC1) or 3V_(T)), and the logic lowcomparison data value has a voltage of 0 Volts. If the comparison datavalue matches the data value stored in CAM cell 1000, then a voltage of0 Volts is applied to node N3. Under these conditions, match transistor1190 is turned off, thereby allowing the voltage on match sense line1500 to remain at 0.3 Volts. If the comparison data value does not matchthe data value stored in CAM cell 1000, then a voltage of 0.9 Volts isapplied to node N3. Under these conditions, 1 match transistor 1190turns on, thereby pulling down the voltage on match sense line 1500 downto 0 Volts. Sensor circuit 1300 senses the voltage on match sense line1500, and indicates a no-match condition if match sense line 1500 ispulled down to 0 Volts, and indicates a match condition if match senseline 1500 remains at 0.3 Volts. Because the full signal swing on matchsense line 1500 is equal to 0.3 Volts, and because the bit line controlcircuit 1200 is powered by the V_(CC1) supply voltage, the powerrequirements of a compare operation are advantageously very low in CAMcell 1000.

Local masking signal LM#₁ is an active low signal. If the local maskingsignal LM#₁ has a logic low value, local masking transistor 1180 isturned off, thereby isolating match sense lines 1500 and 1510. Underthese conditions, match sense line is maintained at 0.3 Volts,regardless of the results of the comparison within CAM cell 1000. CAMcell 1000 therefore performs as if a match condition exists, regardlessof the results of the comparison within CAM cell 1000. In this manner,local masking transistor 1180 enables CAM cell 1000 to be effectivelymasked from the comparison operation. Although FIG. 8 indicates thatlocal masking transistor 1180 is coupled between match transistor 1190and match sense line 1510, it is understood that local maskingtransistor 1180 can be coupled between match transistor 1190 and matchsense line 1500 to achieve similar results.

FIG. 9 is a schematic diagram of sensor circuit 1300. Because sensorcircuit 1300 is similar to sensor circuit 130 (FIG. 5), similar elementsin FIGS. 5 and 9 are labeled with similar reference numbers. Sensorcircuit 1300 eliminates transistor 515 of sensor circuit 130, such thatthe source of transistor 514 is connected to ground. Sensor circuit 1300further includes n-channel transistor 516, which is connected in seriesacross match lines 1500 and 1510. The gate of transistor 516 isconnected to the output terminal of inverter 501. Sensor circuit 1500also includes n-channel transistor 517, which is connected between matchsense line 1510 and the ground supply terminal. The gate of transistor517 is coupled to receive the CLK2 signal.

During a pre-charge period before the compare operation is performed,the CLK1 and CLK2 signals have logic low values. The logic low CLK2signal causes transistor 511 to turn on, thereby coupling the V_(CC1)supply voltage to the drain of transistor 513. In the described example,the V_(CC1) supply voltage is equal to approximately three times thethreshold voltage of an n-channel transistor, or about 0.9 Volts. Thelogic low CLK1 signal causes NAND gate 505 to provide a logic highoutput signal (e.g., 2.5 Volts) to the gate of transistor 512, therebyturning on this transistor. As a result, transistor 512 also helps topull up the voltage on the drain of transistor 513 to the V_(CC1) supplyvoltage.

Under these conditions, transistor 514 is turned on by current source504. Transistor 514 has a threshold voltage of 0.3 Volts. As a result,the voltage on match sense line 1500 is held at 0.3 Volts. The logic lowCLK2 signal causes transistor 516 to turn on, thereby coupling matchsense lines 1500 and 1510. Consequently, match sense line 1510 is alsoheld at 0.3 Volts.

The compare operation begins when the CLK2 signal goes high. The logichigh CLK2 signal causes transistors 511 and 516 to be turned off. TheCLK2 signal transitions in a logic high state shortly before the CLK1signal transitions to a logic high state. As a result, the output signalprovided by NAND gate 505 remains high for a short time after the CLK2signal goes high. This ensures that transistor 512 remains on while theCLK2 signal goes high, thereby preventing noise conditions from pullingdown the voltage on match sense line 1500. The CLK1 signal thentransitions to a logic high value, such that the output voltage providedby NAND gate 505 is determined by the state of the voltage on matchsense line 1500. At this time, node N3 is either pulled up to 0.9 Volts(if a no-match condition exists) or pulled down to 0 Volts (if a matchcondition exists).

As previously described, during a no-match condition node N3 will becoupled to a comparison bit line having a voltage of 0.9 Volts througheither transistor 116 or transistor 117. Under these conditions, matchtransistor 1190 turns on, and current flows through transistor 513. Thiscurrent is greater than the current provided by current source 503. As aresult, the voltage of match sense line 1500 is pulled down to 0 Volts.The 0 Volt signal on match sense line 1500 causes the voltage on thegate of transistor 513 to be pulled up to the V_(CC) supply voltage(e.g., 2.5 Volts) by current source 304. This V_(CC) supply voltagerepresents a logic high input signal to NAND gate 505. Consequently,NAND gate 505 provides a logic low output signal to the gate oftransistor 512. As a result, transistor 512 is turned off, therebypreventing DC current flow through transistor 513.

The logic low output of NAND gate 505 is also provided to inverter 502.In response, inverter 502 provides a logic high output signal having avoltage equal to the V_(CC) supply voltage (e.g., 2.5 Volts). Thisoutput signal is used to indicate a no-match condition to an encodercircuit (not shown).

As described above, during a match condition node N3 will be coupled toa comparison bit line having a voltage of 0 Volts through eithertransistor 116 or transistor 117. As a result, no current flows throughtransistor 513. Consequently, the gate of transistor 513 is maintainedat about 0.3 Volts. This 0.3 Volt signal represents a logic low inputsignal to NAND gate 505. As a result, NAND gate 505 provides a logichigh output signal to transistor 512. Transistor 512 therefore remainson (even though there is no current flow). If the signal on match senseline 1500 is pulled low by noise, then current source 503 will pull thevoltage on match sense line 1500 back up to 0.3 Volts through turned ontransistor 512.

The logic high output of NAND gate 505 is also provided to inverter 502.In response, inverter 502 provides a logic low output signal having avoltage equal to 0 Volts. This output signal is used to indicate a matchcondition to an encoder circuit (not shown).

Although the operation of sensor circuit 1300 has been described inconnection with a single CAM cell 1000, it is understood that a matchcondition must exist in all of the CAM cells coupled to match sense line1500 in order for sensor circuit 1300 to provide a logic low outputsignal to the encoder. Conversely, if a no-match condition exists in anyone of the CAM cells coupled to match sense line 1500, then sensorcircuit 1300 will provide a logic high output signal to the encoder.

Although the present invention has been described in connection withparticular embodiments, other embodiments are possible and areconsidered to be within the scope of the present invention. FIG. 10A isa schematic diagram of an 8-T CAM cell 800A in accordance with onevariation of the present invention. Similar elements in CAM cell 1000(FIG. 8) and CAM cell 800A are labeled with similar reference numbers.CAM cell 800A includes the same elements as CAM cell 1000, with theexception of access transistor 115 and bit line 102, which are notpresent in CAM cell 800A. CAM cell 800A is written and read through bitline 101 and access transistor 114. The compare operation of CAM cell800A is identical to the compare operation of CAM cell 1000. CAM cell800A advantageously uses one less transistor and one less bit line thanCAM cell 1000. Note that the above-described variations of CAM cell 1000can also be applied to CAM cell 800A.

FIG. 10B is a schematic diagram of an 8-T CAM cell 800B in accordancewith another variation of the present invention. Similar elements in CAMcell 1000 (FIG. 8) and CAM cell 800B are labeled with similar referencenumbers. CAM cell 800B includes the same elements as CAM cell 1000, withthe exception of access transistor 115 and bit lines 102 and 103, whichare not present in CAM cell 800B. CAM cell 800B is written and readthrough bit line 101 and access transistor 114. The compare operation ofCAM cell 800B is similar to the compare operation of CAM cell 1000.However, the comparison data value CD₀# is provided on bit line 101 inthis variation. Selection circuitry (not shown) is provided toselectively couple bit line 101 to the above-described column selectcircuitry (not shown) during a read or a write operation, or to the bitline control circuit 120 during a compare operation. CAM cell 800Badvantageously uses one fewer transistor and two fewer bit lines thanCAM cell 1000. Note that the above-described variations of CAM cell 1000can also be applied to CAM cell 800B.

Although the present invention has been described in connection withseveral embodiments, it is understood that this invention is not limitedto the embodiments disclosed, but is capable of various modificationswhich would be apparent to one of ordinary skill in the art. Thus, theinvention is limited only by the following claims.

1. A content addressable memory (CAM) cell comprising: a static randomaccess memory (SRAM) cell that operates in response to a V_(CC) supplyvoltage, the SRAM cell storing a data value; a first set of one or morebit lines coupled to the SRAM cell, wherein the data value is written toand read from the SRAM cell on the first set bit lines, the first set ofbit lines having a signal swing equal to the V_(CC) supply voltage; anda second set of bit lines coupled to receive a comparison data value,the second set of bit lines having a signal swing less than the V_(CC)supply voltage.
 2. The CAM cell of claim 1, further comprising a circuitfor comparing the data value with the comparison data value to determinewhether a match exists.
 3. The CAM cell of claim 2, wherein the circuitcomprises: a first transistor having a gate coupled to receive a signalrepresentative of the data value; and a second transistor having a gatecoupled to receive a signal representative of the inverse of the datavalue.
 4. The CAM cell of claim 3, wherein the second set of bit linescomprises: a first bit line coupled to a source region of the firsttransistor; and a second bit line coupled to a source region of thesecond transistor.
 5. The CAM cell of claim 4, wherein a drain region ofthe first transistor is coupled to a drain region of the secondtransistor at a first node.
 6. The CAM cell of claim 5, furthercomprising a diode element coupled to the first node.
 7. The CAM cell ofclaim 6, further comprising a local mask transistor coupled in serieswith the diode element.
 8. The CAM cell of claim 6, wherein the diodeelement comprises a diode-connected transistor.
 9. The CAM cell of claim6, wherein the diode element comprises a P-N junction.
 10. The CAM cellof claim 6, further comprising a match line coupled to the diodeelement, wherein the diode element is forward biased from the match lineto the first node.
 11. The CAM cell of claim 10, wherein the match linehas a signal swing equal to a transistor threshold voltage.
 12. The CAMcell of claim 10, further comprising a sensor circuit coupled to thematch line, the sensor circuit pre-charging the match line to a voltageless than the V_(CC) supply voltage.
 13. The CAM cell of claim 12,wherein the sensor circuit comprises a logic gate for providing anoutput signal that indicates whether a match or a no-match conditionexists, the output signal having a signal swing equal to the V_(CC)supply voltage.
 14. The CAM cell of claim 1, further comprising a bitline control circuit for biasing the second set of bit lines.
 15. TheCAM cell of claim 14, wherein the bit line control circuit comprises afirst transistor for coupling the second set of bit lines during apre-charge operation.
 16. The CAM cell of claim 14, wherein the bitcontrol circuit comprises one or more transistors for coupling thesecond set of bit lines to a voltage supply line during a global maskingoperation, the voltage supply line having a voltage less than the V_(CC)supply voltage.
 17. The CAM cell of claim 14, wherein the bit linecontrol circuit comprises a plurality of transistors for selectivelycoupling the second set of bit lines to a voltage supply line and aground supply line, whereby the second set of bit lines receive voltagesrepresentative of the comparison data value from the voltage supply lineand the ground supply line, the voltage supply line having a voltageless than the V_(CC) supply voltage.
 18. The CAM cell of claim 17,wherein the voltage supply line has a voltage of two times a transistorthreshold voltage.
 19. The CAM cell of claim 14, wherein the bit linecontrol circuit is powered by a supply voltage less than the V_(CC)supply voltage.
 20. A content addressable memory (CAM) cell having amatch line that carries a signal to indicate whether a match or ano-match condition exists within the CAM cell, wherein the differencebetween a voltage on the match line during the match condition and avoltage on the the match line during the no-match condition in equal toone transistor threshold voltage.
 21. A method of operating a contentaddressable memory (CAM) cell that includes a static random access(SRAM) cell, the method comprising: operating the SRAM cell in responseto a V_(CC) supply voltage, the SRAM cell storing a data value; writinga data value to the SRAM cell on a first set of one or more bit lines,the first set of bit lines having a signal swing equal to the V_(CC)supply voltage; reading data values from the SRAM cell on the first setof bit lines; controlling the signal swing on the first set of bit linesto be equal to the V_(CC) supply voltage; providing comparison datavalues to the CAM cell on a second set of bit lines; and controlling thesignal swing on the second set of bit lines to be less than the V_(CC)supply voltage.
 22. The method of claim 21, further comprising the stepof comparing the data value stored in the CAM cell with the comparisondata value to determine whether a match condition or a no-matchcondition exists.
 23. The method of claim 22, further comprising thestep of indicating a match condition and a no-match audition byproviding a signal having a signal swing equal to one transistorthreshold voltage.
 24. The method of claim 22, wherein the step ofcomparing comprises the step of coupling one of the bit lines in thesecond set of bit lines to a match line in response to the data valuestored in the CAM cell.
 25. The method of claim 24, further comprisingthe step of pre-charging the match line to a voltage less than theV_(CC) supply voltage.
 26. The method of claim 25, further comprisingthe step of discharging the match line when a no-match condition exists.27. The method of claim 23, further comprising the step of convertingthe signal having the signal swing of one transistor threshold voltageto a signal having a signal swing equal to the V_(CC) supply voltage.28. The method of claim 21, further comprising the step of equalizingthe second set of bit lines prior to providing the comparison datavalues to the CAM cell on the second set of bit lines.
 29. The method ofclaim 21, further comprising the step of connecting the second set ofbit lines to a voltages supply line during a global masking operation,the voltage supply line having a voltage less than the V_(CC) supplyvoltage.
 30. The method of claim 21, further comprising the step ofselectively coupling the second set of bit lines to a voltage supplyline and a ground supply line, whereby the second set of bit linesreceive voltages representative of the comparison data value from thevoltage supply line and the ground supply line, the voltage supply linehaving a voltage less than the V_(CC) supply voltage.
 31. The method ofclaim 30, wherein the voltage supply line has a voltage of two times atransistor threshold voltage.
 32. The method of claim 21, furthercomprising the step of biasing the second set of bit lines with a supplyvoltage less than the V_(CC) supply voltage.
 33. A method of operating acontent addressable memory (CAM) array, comprising the steps of:precharging first and second match sense lines that are electricallycoupled to compare circuitry within a row of CAM cells to first andsecond positive voltage levels, respectively, said second voltage levelhaving a maximum value that is less than Vcc, where Vcc is a powersupply voltage supplied to the row of CAM cells; applying a plurality ofcomparison data values to a plurality of comparison data lines that areelectrically coupled to the row of CAM cells; and detecting amatch/no-match condition between the applied comparison data values anddata stored in the row of CAM cells by sensing a voltage on the firstmatch sense line in-sync with discharging the second match sense linefrom its precharged second positive voltage level.
 34. The method ofclaim 33, wherein said detecting step comprises shorting the prechargedfirst match sense line to the discharged second match sense line if ano-match condition is present between the applied comparison data valuesand the data stored in the row of CAM cells.
 35. The method of claim 33,wherein the row of CAM cells is electrically coupled to a plurality ofread/write bit lines; wherein said precharging step is preceded by thestep of writing data into the row of CAM cells by driving at least someof the plurality of read/write bit lines at high logic levels that areabout equal to Vcc; and wherein said applying step comprises driving atleast some of the comparison data lines at high logic levels that arelower than Vcc by an amount equal to at least a transistor thresholdvoltage.
 36. A content addressable memory (CAM) array, comprising thesteps of: a plurality of pairs of comparison data lines; a row of CAMcells having compare circuitry therein that is electrically coupled tosaid plurality of pairs of comparison data lines; first and second matchsense lines that are electrically coupled to the compare circuitry insaid row of CAM cells; and a sensor circuit that is configured todisable the compare circuitry from indicating a match/no-match conditionon the first match sense line by precharging the first and second matchsense lines to first and second positive voltage levels, respectively,and is further configured to enable the compare circuitry to indicate amatch/no-match condition on the first match sense line by dischargingthe second match sense line from its precharged second positive voltagelevel, said second positive voltage level having a maximum value that isless than Vcc by at least a transistor threshold voltage, where Vcc is apower supply voltage supplied to said row of CAM cells.
 37. The CAMarray of claim 36, wherein said sensor circuit is further configured todetect a voltage on the first match sense line as representing thematch/no-match condition, in response to discharging the second matchsense line from its precharged second positive voltage level.
 38. TheCAM array of claim 37, wherein an output of said sensor circuit iselectrically coupled to an encoder.
 39. The CAM array of claim 37,wherein said sensor circuit is responsive to at least one clock signal.40. The CAM array of claim 37, wherein in response to being enabled bysaid sensor circuit, the compare circuitry is configured to short thefirst match sense line to the discharged second match sense line if ano-match condition is present between data applied to said plurality ofpairs of comparison data lines and data entry stored in said row of CAMcells.
 41. The CAM array of claim 37, wherein the compare circuitrycomprises a plurality of local masking transistors having first currentcarrying terminals electrically connected to the second match senseline.
 42. The CAM array of claim 41, wherein said row of CAM cellscomprises SRAM-based memory cells therein; and wherein the local maskingtransistors are responsive to local mask enable signals.
 43. The CAMarray of claim 42, further comprising a plurality of pairs of read/writebit lines electrically coupled to the SRAM-based memory cells in saidrow of CAM cells.
 44. The CAM array of claim 37, wherein the comparecircuitry comprises a plurality of local masking transistors havingfirst current carrying terminals electrically connected to the firstmatch sense line.
 45. The CAM array of claim 44, wherein said row of CAMcells comprises SRAM-based memory cells therein; and wherein the localmasking transistors are responsive to local mask enable signals.
 46. TheCAM array of claim 45, further comprising a plurality of pairs ofread/write bit lines electrically coupled to the SRAM-based memory cellsin said row of CAM cells.
 47. The CAM array of claim 36, wherein thecompare circuitry comprises a plurality of XOR gates that are eachassociated with a respective CAM cell in said row of CAM cells.
 48. Amethod of operating a content addressable memory (CAM) cell, comprisingthe steps of: precharging first and second match sense lines that areelectrically coupled to a compare circuit within the CAM cell to firstand second positive voltage levels, respectively, said second positivevoltage level having a maximum value that is less than Vcc, where Vcc isa power supply voltage supplied to the CAM cell; applying a comparisondata value to a pair of comparison data lines that are electricallycoupled to the CAM cell; and comparing the applied comparison data valuewith a data value stored in the CAM cell by discharging the second matchsense line from its precharged second positive voltage level to adischarged voltage level and then sensing whether the first match senseline is maintained at its precharged first positive voltage level or ispulled down to the discharged voltage level by the compare circuit. 49.The method of claim 48, wherein said precharging step is performedin-sync with a first edge to a first clock signal; and wherein saidcomparing step is performed in-sync with a second edge of the firstclock signal.
 50. The method of claim 48, wherein the first and secondpositive voltage levels are equal.
 51. The method of claim 50, whereinsaid applying step comprises driving at least one of the pair ofcomparison data lines with a signal having a voltage swing that is lessthan Vcc.
 52. The method of claim 48, wherein said comparing stepcomprises shorting the first match sense line to the discharged secondmatch sense line in the event a no-match condition exists between theapplied comparison data value and the data value stored in the CAM cell.53. The CAM array of claim 36, further comprising: a plurality of pairsof read/write bit lines that are electrically coupled to the CAM cellsin said row of CAM cells; and a bit line control circuit electricallycoupled to said plurality of pairs of comparison data lines and saidplurality of pairs of read/write bit lines, said bit line controlcircuit configured to support signal swings on said plurality of pairsof comparison data lines that are less than signal swings on saidplurality of pairs of read/write bit lines.
 54. The CAM array of claim53, wherein the signal swings on said plurality of pairs of read/writebit lines are equal to about Vcc.
 55. A CAM array, comprising: a CAMcell having a memory cell therein that is powered at a supply voltage; apair of read/write bit lines electrically coupled to said CAM cell; apair of comparison data lines electrically coupled to said CAM cell; anda bit line control circuit electrically coupled to said pair ofread/write bit lines and said pair of comparison bit lines, said bitline control circuit configured to support a signal swing on said pairof comparison bit lines that is less than a signal swing on said pair ofread/write bit lines.
 56. A CAM cell, comprising: a memory cellelectrically coupled to a pair of read/write bit lines; and a datacomparison circuit electrically coupled to a pair of comparison bitlines, a match line and said memory cell, said data comparison circuitconfigured to indicate a mismatch between data stored in said memorycell and data applied to the pair of comparison bit lines during acomparison operation, by transferring charge between the match line andat least one of the pair of comparison bit lines.
 57. The CAM cell ofclaim 56, wherein said data comparison circuit comprises a pair ofN-channel transistors that are electrically connected in series betweenthe pair of comparison bit lines.
 58. The CAM cell of claim 57, whereingate terminals of the pair of N-channel transistors are electricallycoupled to said memory cell.
 59. The CAM cell of claim 58, wherein thepair of N-channel transistors are joined together at a node; and whereinsaid data comparison circuit further comprises a first transistor havingfirst current carrying terminal electrically coupled to the node. 60.The CAM cell of claim 59, wherein said data comparison circuit furthercomprises a local masking transistor having a first current carryingterminal electrically connected to the first transistor and a secondcurrent carrying terminal electrically connected to the match line. 61.A CAM array, comprising: a first CAM cell comprising a first memory cellelectrically coupled to a first pair of read/write bit lines, and afirst data comparison circuit electrically coupled to a first pair ofcomparison bit lines, a match line and said first memory cell, saidfirst data comparison circuit configured to indicate a mismatch betweendata stored in said first memory cell and data applied to the first pairof comparison bit lines during a comparison operation, by transferringcharge between the match line and at least one of the first pair ofcomparison bit lines; and a second CAM cell comprising a second memorycell electrically coupled to a second pair of read/write bit lines, anda second data comparison circuit electrically coupled to a second pairof comparison bit lines, the match line and said second memory cell,said second data comparison circuit configured to indicate a mismatchbetween data stored in said second memory cell and data applied to thesecond pair of comparison bit lines during the comparison operation, bytransferring charge between the match line and at least one of thesecond pair of comparison bit lines.
 62. The CAM array of claim 61,wherein the first data comparison circuit comprises a first pair ofN-channel transistors that are electrically connected in series betweenthe first pair of comparison bit lines; and wherein the second datacomparison circuit comprises a second pair of N-channel transistors thatare electrically connected in series between the second pair ofcomparison bit lines.
 63. The CAM array of claim 62, wherein gateterminals of the first pair of N-channel transistors are electricallycoupled to the first memory cell.
 64. The CAM array of claim 62, whereinthe first pair of N-channel transistors are joined together at a firstnode; and wherein the first data comparison circuit further comprises afirst transistor having a first current carrying terminal electricallycoupled to the first node.
 65. The CAM array of claim 64, wherein thesecond pair of N-channel transistors are joined together at a secondnode; and wherein the second data comparison circuit further comprises asecond transistor having a first current carrying terminal electricallycoupled to the second node.
 66. The CAM array of claim 65, furthercomprising a sensor circuit having an output that is electricallycoupled to gate terminals of the first and second transistors.
 67. TheCAM array of claim 64, wherein said first data comparison circuitfurther comprises a local masking transistor having a first currentcarrying terminal electrically connected to the first transistor and asecond current carrying terminal electrically connected to the matchline.
 68. A CAM cell, comprising: a memory cell electrically coupled toa pair of read/write bit lines; and a data comparison circuitelectrically coupled to a pair of comparison bit lines, a match line andsaid memory cell, said data comparison circuit configured to indicate amismatch between data stored in said memory cell and data applied to thepair of comparison bit lines during a comparison operation, by sinkingcurrent from the match line to at least one of the pair of comparisonbit lines.